搜索资源列表
zynq_base_trd_14_3
- xilinx的视频处理参考Verilog代码-Video Targeted Reference Design On Xilinx FPGA With Verilog
pal.rar
- PAL制式时序发生verilog模块，13.5MHz，频率可以改,PAL video timing generator verilog modules, 13.5MHz, the frequency can be changed
DE2_70_TV
- de2 70 开发板的演示程序，verilog语言编写，视频输入输出-de2 70 development board demo program, verilog language written, video input and output
qugehang
- 用verilog代码实现视频去隔行，功能强大，有必要的注释-Video Deinterlacing
eetop.cn_quartus_pgm
- verilog基本语法 入门的视频教程 flash的-verilog basic syntax of introductory video tutorials flash
bluespec-h264_latest.tar
- H.264硬件视频解码，采用verilog代码设计，支持1.5M时钟下30bps的QCIF分辨率的实时视频解码-H. 264 hardware video decoder, use verilog code design, support under 1.5 M clock 30 BPS QCIF resolution of real-time video decoding
ColorBar
- verilog 视频领域 黑场信号产生-verilog field of video black burst signal is generated
tequan
- 特权同学 深入浅出玩转FPGA视频教程里面的verilog代码-Fun privileged classmates easy video tutorials inside FPGA verilog code
LCD1602-TEST
- 利用verilog驱动LCD1602 本实验是用LCD1602显示英文。（LCD带字库）-//Use verilog driver LCD1602// video tutorial for all of us 21EDA e-learning board// The experiment is LCD1602 display in English. (LCD with font)
BT656
- BT656资料中文版，可用于视频编解码，支持verilog等工具使用-BT656 information Chinese version can be used for video encoding and decoding, and other tools used to support verilog
bt1120p_gen
- bt1120时序生成，verilog程序，1920x1080p60分辨率-synchronized video timing generation itu bt1120 within verilog program, 1920x1080p60 resolution
10_CMOS_OV7725_RGB640480
- 采用FPGA EP4CE开发的OV7725摄像头视频采集系统，采用Verilog实现-Using FPGA EP4CE developed OV7725 camera video capture system, using Verilog realize
Verilog_prj
- 特权同学BJ-EPM240 CPLD开发板配套视频源码文件，ex1~ex15全，是入门Verilog的首选。-Privileged students BJ-EPM240 CPLD development board supporting the video source files, ex1 ~ ex15 whole, is the first choice of entry Verilog.
ov7670-1
- ov7670摄像头FPGA数据采集、显示模块，测试可用-ov7670 camera, verilog code, video capture and display
02_VGA_VIP_YCbCr422_RGB888
- 用Verilog语言实现的视频源YCbCr422转为RGB888的算法，只用三个时钟完成-Verilog language to achieve the video source YCbCr422 to RGB888 algorithm, using only three clock
video_add_program
- 基于verilog语言通过SPI通信实现视频叠加系统 -Video overlay system based on Verilog through SPI
DCT
- 用Verilog HDL编写的离散余弦变换，可用于视频图像压缩，并在modelsim SE6.0中仿真通过-Verilog HDL prepared with discrete cosine transform can be used for video image compression, and modelsim SE6.0 simulation through
7_to_1-LVDS-dispaly-from-FLASH
- 该代码是基于verilog 实现的代码，可以用于对接受1080P的LVDS视频数据并处理后显示到各种规格的LCD屏幕上，且支持从FLASH中读取BMP的图片数据并实时显示到LCS屏幕-The code is based on the code verilog achieve, it can be used for receiving LVDS 1080P video and data processing displayed on a variety of LCD screen, and sup
OV7670_VGA
- verilog写的VGA视频处理代码,里面有完整的工程项目-Written by verilog VGA video processing code
IDCT
- HEVC是正在研发的新一代视频编码标准。 本文面向HDTV应用，设计兼容HEVC标准的两位整数IDCT电路， 通过对IDCT的特点进行分析，完成了电路的架构设计, 采用较为节省面积的做法和流水线结构，并进行VerilogHDL代码设计-High Efficiency Video Coding(HEVC) is the currently developing video standard. In this article, a novel pipelined 2-D IDCT architect